922 lines
20 KiB
C
922 lines
20 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Neskovic <neskovic@compeng.uni-frankfurt.de>.
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*/
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/*
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* USER API:
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*
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* Kernel fpu methods:
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* kfpu_allowed()
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* kfpu_begin()
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* kfpu_end()
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* kfpu_init()
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* kfpu_fini()
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*
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* SIMD support:
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*
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* Following functions should be called to determine whether CPU feature
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* is supported. All functions are usable in kernel and user space.
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* If a SIMD algorithm is using more than one instruction set
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* all relevant feature test functions should be called.
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*
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* Supported features:
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* zfs_sse_available()
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* zfs_sse2_available()
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* zfs_sse3_available()
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* zfs_ssse3_available()
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* zfs_sse4_1_available()
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* zfs_sse4_2_available()
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*
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* zfs_avx_available()
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* zfs_avx2_available()
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*
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* zfs_bmi1_available()
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* zfs_bmi2_available()
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*
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* zfs_avx512f_available()
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* zfs_avx512cd_available()
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* zfs_avx512er_available()
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* zfs_avx512pf_available()
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* zfs_avx512bw_available()
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* zfs_avx512dq_available()
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* zfs_avx512vl_available()
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* zfs_avx512ifma_available()
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* zfs_avx512vbmi_available()
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*
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* NOTE(AVX-512VL): If using AVX-512 instructions with 128Bit registers
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* also add zfs_avx512vl_available() to feature check.
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*/
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#ifndef _SIMD_X86_H
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#define _SIMD_X86_H
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#include <sys/isa_defs.h>
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/* only for __x86 */
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#if defined(__x86)
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#include <sys/types.h>
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#if defined(_KERNEL)
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#include <asm/cpufeature.h>
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#else
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#include <cpuid.h>
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#endif
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#if defined(_KERNEL)
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/*
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* Disable the WARN_ON_FPU() macro to prevent additional dependencies
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* when providing the kfpu_* functions. Relevant warnings are included
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* as appropriate and are unconditionally enabled.
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*/
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#if defined(CONFIG_X86_DEBUG_FPU) && !defined(KERNEL_EXPORTS_X86_FPU)
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#undef CONFIG_X86_DEBUG_FPU
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#endif
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#if defined(HAVE_KERNEL_FPU_API_HEADER)
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#include <asm/fpu/api.h>
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#include <asm/fpu/internal.h>
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#else
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#include <asm/i387.h>
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#include <asm/xcr.h>
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#endif
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/*
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* The following cases are for kernels which export either the
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* kernel_fpu_* or __kernel_fpu_* functions.
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*/
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#if defined(KERNEL_EXPORTS_X86_FPU)
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#define kfpu_allowed() 1
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#define kfpu_init() 0
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#define kfpu_fini() ((void) 0)
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#if defined(HAVE_UNDERSCORE_KERNEL_FPU)
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#define kfpu_begin() \
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{ \
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preempt_disable(); \
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__kernel_fpu_begin(); \
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}
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#define kfpu_end() \
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{ \
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__kernel_fpu_end(); \
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preempt_enable(); \
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}
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#elif defined(HAVE_KERNEL_FPU)
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#define kfpu_begin() kernel_fpu_begin()
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#define kfpu_end() kernel_fpu_end()
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#else
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/*
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* This case is unreachable. When KERNEL_EXPORTS_X86_FPU is defined then
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* either HAVE_UNDERSCORE_KERNEL_FPU or HAVE_KERNEL_FPU must be defined.
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*/
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#error "Unreachable kernel configuration"
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#endif
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#else /* defined(KERNEL_EXPORTS_X86_FPU) */
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/*
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* When the kernel_fpu_* symbols are unavailable then provide our own
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* versions which allow the FPU to be safely used.
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*/
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#if defined(HAVE_KERNEL_FPU_INTERNAL)
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#include <linux/mm.h>
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extern union fpregs_state **zfs_kfpu_fpregs;
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/*
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* Initialize per-cpu variables to store FPU state.
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*/
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static inline void
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kfpu_fini(void)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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if (zfs_kfpu_fpregs[cpu] != NULL) {
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free_pages((unsigned long)zfs_kfpu_fpregs[cpu],
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get_order(sizeof (union fpregs_state)));
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}
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}
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kfree(zfs_kfpu_fpregs);
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}
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static inline int
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kfpu_init(void)
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{
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zfs_kfpu_fpregs = kzalloc(num_possible_cpus() *
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sizeof (union fpregs_state *), GFP_KERNEL);
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if (zfs_kfpu_fpregs == NULL)
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return (-ENOMEM);
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/*
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* The fxsave and xsave operations require 16-/64-byte alignment of
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* the target memory. Since kmalloc() provides no alignment
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* guarantee instead use alloc_pages_node().
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*/
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unsigned int order = get_order(sizeof (union fpregs_state));
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int cpu;
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for_each_possible_cpu(cpu) {
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struct page *page = alloc_pages_node(cpu_to_node(cpu),
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GFP_KERNEL | __GFP_ZERO, order);
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if (page == NULL) {
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kfpu_fini();
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return (-ENOMEM);
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}
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zfs_kfpu_fpregs[cpu] = page_address(page);
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}
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return (0);
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}
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#define kfpu_allowed() 1
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#define ex_handler_fprestore ex_handler_default
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/*
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* FPU save and restore instructions.
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*/
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#define __asm __asm__ __volatile__
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#define kfpu_fxsave(addr) __asm("fxsave %0" : "=m" (*(addr)))
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#define kfpu_fxsaveq(addr) __asm("fxsaveq %0" : "=m" (*(addr)))
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#define kfpu_fnsave(addr) __asm("fnsave %0; fwait" : "=m" (*(addr)))
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#define kfpu_fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
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#define kfpu_fxrstorq(addr) __asm("fxrstorq %0" : : "m" (*(addr)))
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#define kfpu_frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
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#define kfpu_fxsr_clean(rval) __asm("fnclex; emms; fildl %P[addr]" \
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: : [addr] "m" (rval));
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static inline void
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kfpu_save_xsave(struct xregs_state *addr, uint64_t mask)
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{
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uint32_t low, hi;
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int err;
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low = mask;
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hi = mask >> 32;
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XSTATE_XSAVE(addr, low, hi, err);
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WARN_ON_ONCE(err);
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}
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static inline void
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kfpu_save_fxsr(struct fxregs_state *addr)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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kfpu_fxsave(addr);
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else
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kfpu_fxsaveq(addr);
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}
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static inline void
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kfpu_save_fsave(struct fregs_state *addr)
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{
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kfpu_fnsave(addr);
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}
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static inline void
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kfpu_begin(void)
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{
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/*
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* Preemption and interrupts must be disabled for the critical
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* region where the FPU state is being modified.
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*/
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preempt_disable();
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local_irq_disable();
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/*
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* The current FPU registers need to be preserved by kfpu_begin()
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* and restored by kfpu_end(). They are stored in a dedicated
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* per-cpu variable, not in the task struct, this allows any user
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* FPU state to be correctly preserved and restored.
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*/
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union fpregs_state *state = zfs_kfpu_fpregs[smp_processor_id()];
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if (static_cpu_has(X86_FEATURE_XSAVE)) {
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kfpu_save_xsave(&state->xsave, ~0);
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} else if (static_cpu_has(X86_FEATURE_FXSR)) {
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kfpu_save_fxsr(&state->fxsave);
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} else {
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kfpu_save_fsave(&state->fsave);
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}
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}
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static inline void
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kfpu_restore_xsave(struct xregs_state *addr, uint64_t mask)
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{
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uint32_t low, hi;
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low = mask;
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hi = mask >> 32;
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XSTATE_XRESTORE(addr, low, hi);
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}
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static inline void
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kfpu_restore_fxsr(struct fxregs_state *addr)
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{
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/*
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* On AuthenticAMD K7 and K8 processors the fxrstor instruction only
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* restores the _x87 FOP, FIP, and FDP registers when an exception
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* is pending. Clean the _x87 state to force the restore.
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*/
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if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK)))
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kfpu_fxsr_clean(addr);
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if (IS_ENABLED(CONFIG_X86_32)) {
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kfpu_fxrstor(addr);
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} else {
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kfpu_fxrstorq(addr);
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}
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}
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static inline void
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kfpu_restore_fsave(struct fregs_state *addr)
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{
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kfpu_frstor(addr);
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}
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static inline void
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kfpu_end(void)
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{
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union fpregs_state *state = zfs_kfpu_fpregs[smp_processor_id()];
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if (static_cpu_has(X86_FEATURE_XSAVE)) {
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kfpu_restore_xsave(&state->xsave, ~0);
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} else if (static_cpu_has(X86_FEATURE_FXSR)) {
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kfpu_restore_fxsr(&state->fxsave);
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} else {
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kfpu_restore_fsave(&state->fsave);
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}
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local_irq_enable();
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preempt_enable();
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}
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#else
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/*
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* FPU support is unavailable.
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*/
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#define kfpu_allowed() 0
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#define kfpu_begin() do {} while (0)
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#define kfpu_end() do {} while (0)
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#define kfpu_init() 0
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#define kfpu_fini() ((void) 0)
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#endif /* defined(HAVE_KERNEL_FPU_INTERNAL) */
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#endif /* defined(KERNEL_EXPORTS_X86_FPU) */
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#else /* defined(_KERNEL) */
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/*
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* FPU dummy methods for user space.
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*/
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#define kfpu_allowed() 1
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#define kfpu_begin() do {} while (0)
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#define kfpu_end() do {} while (0)
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#endif /* defined(_KERNEL) */
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/*
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* CPUID feature tests for user-space. Linux kernel provides an interface for
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* CPU feature testing.
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*/
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#if !defined(_KERNEL)
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/*
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* x86 registers used implicitly by CPUID
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*/
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typedef enum cpuid_regs {
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EAX = 0,
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EBX,
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ECX,
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EDX,
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CPUID_REG_CNT = 4
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} cpuid_regs_t;
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/*
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* List of instruction sets identified by CPUID
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*/
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typedef enum cpuid_inst_sets {
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SSE = 0,
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SSE2,
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SSE3,
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SSSE3,
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SSE4_1,
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SSE4_2,
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OSXSAVE,
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AVX,
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AVX2,
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BMI1,
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BMI2,
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AVX512F,
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AVX512CD,
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AVX512DQ,
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AVX512BW,
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AVX512IFMA,
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AVX512VBMI,
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AVX512PF,
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AVX512ER,
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AVX512VL,
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AES,
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PCLMULQDQ
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} cpuid_inst_sets_t;
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/*
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* Instruction set descriptor.
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*/
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typedef struct cpuid_feature_desc {
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uint32_t leaf; /* CPUID leaf */
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uint32_t subleaf; /* CPUID sub-leaf */
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uint32_t flag; /* bit mask of the feature */
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cpuid_regs_t reg; /* which CPUID return register to test */
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} cpuid_feature_desc_t;
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#define _AVX512F_BIT (1U << 16)
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#define _AVX512CD_BIT (_AVX512F_BIT | (1U << 28))
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#define _AVX512DQ_BIT (_AVX512F_BIT | (1U << 17))
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#define _AVX512BW_BIT (_AVX512F_BIT | (1U << 30))
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#define _AVX512IFMA_BIT (_AVX512F_BIT | (1U << 21))
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#define _AVX512VBMI_BIT (1U << 1) /* AVX512F_BIT is on another leaf */
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#define _AVX512PF_BIT (_AVX512F_BIT | (1U << 26))
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#define _AVX512ER_BIT (_AVX512F_BIT | (1U << 27))
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#define _AVX512VL_BIT (1U << 31) /* if used also check other levels */
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#define _AES_BIT (1U << 25)
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#define _PCLMULQDQ_BIT (1U << 1)
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/*
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* Descriptions of supported instruction sets
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*/
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static const cpuid_feature_desc_t cpuid_features[] = {
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[SSE] = {1U, 0U, 1U << 25, EDX },
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[SSE2] = {1U, 0U, 1U << 26, EDX },
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[SSE3] = {1U, 0U, 1U << 0, ECX },
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[SSSE3] = {1U, 0U, 1U << 9, ECX },
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[SSE4_1] = {1U, 0U, 1U << 19, ECX },
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[SSE4_2] = {1U, 0U, 1U << 20, ECX },
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[OSXSAVE] = {1U, 0U, 1U << 27, ECX },
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[AVX] = {1U, 0U, 1U << 28, ECX },
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[AVX2] = {7U, 0U, 1U << 5, EBX },
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[BMI1] = {7U, 0U, 1U << 3, EBX },
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[BMI2] = {7U, 0U, 1U << 8, EBX },
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[AVX512F] = {7U, 0U, _AVX512F_BIT, EBX },
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[AVX512CD] = {7U, 0U, _AVX512CD_BIT, EBX },
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[AVX512DQ] = {7U, 0U, _AVX512DQ_BIT, EBX },
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[AVX512BW] = {7U, 0U, _AVX512BW_BIT, EBX },
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[AVX512IFMA] = {7U, 0U, _AVX512IFMA_BIT, EBX },
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[AVX512VBMI] = {7U, 0U, _AVX512VBMI_BIT, ECX },
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[AVX512PF] = {7U, 0U, _AVX512PF_BIT, EBX },
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[AVX512ER] = {7U, 0U, _AVX512ER_BIT, EBX },
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[AVX512VL] = {7U, 0U, _AVX512ER_BIT, EBX },
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[AES] = {1U, 0U, _AES_BIT, ECX },
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[PCLMULQDQ] = {1U, 0U, _PCLMULQDQ_BIT, ECX },
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};
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/*
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* Check if OS supports AVX and AVX2 by checking XCR0
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* Only call this function if CPUID indicates that AVX feature is
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* supported by the CPU, otherwise it might be an illegal instruction.
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*/
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static inline uint64_t
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xgetbv(uint32_t index)
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{
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uint32_t eax, edx;
|
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/* xgetbv - instruction byte code */
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__asm__ __volatile__(".byte 0x0f; .byte 0x01; .byte 0xd0"
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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return ((((uint64_t)edx)<<32) | (uint64_t)eax);
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}
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|
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/*
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* Check if CPU supports a feature
|
|
*/
|
|
static inline boolean_t
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__cpuid_check_feature(const cpuid_feature_desc_t *desc)
|
|
{
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uint32_t r[CPUID_REG_CNT];
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|
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if (__get_cpuid_max(0, NULL) >= desc->leaf) {
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/*
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* __cpuid_count is needed to properly check
|
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* for AVX2. It is a macro, so return parameters
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* are passed by value.
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*/
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__cpuid_count(desc->leaf, desc->subleaf,
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r[EAX], r[EBX], r[ECX], r[EDX]);
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return ((r[desc->reg] & desc->flag) == desc->flag);
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}
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return (B_FALSE);
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}
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|
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#define CPUID_FEATURE_CHECK(name, id) \
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static inline boolean_t \
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__cpuid_has_ ## name(void) \
|
|
{ \
|
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return (__cpuid_check_feature(&cpuid_features[id])); \
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}
|
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|
|
/*
|
|
* Define functions for user-space CPUID features testing
|
|
*/
|
|
CPUID_FEATURE_CHECK(sse, SSE);
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CPUID_FEATURE_CHECK(sse2, SSE2);
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CPUID_FEATURE_CHECK(sse3, SSE3);
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CPUID_FEATURE_CHECK(ssse3, SSSE3);
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CPUID_FEATURE_CHECK(sse4_1, SSE4_1);
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CPUID_FEATURE_CHECK(sse4_2, SSE4_2);
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CPUID_FEATURE_CHECK(avx, AVX);
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CPUID_FEATURE_CHECK(avx2, AVX2);
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|
CPUID_FEATURE_CHECK(osxsave, OSXSAVE);
|
|
CPUID_FEATURE_CHECK(bmi1, BMI1);
|
|
CPUID_FEATURE_CHECK(bmi2, BMI2);
|
|
CPUID_FEATURE_CHECK(avx512f, AVX512F);
|
|
CPUID_FEATURE_CHECK(avx512cd, AVX512CD);
|
|
CPUID_FEATURE_CHECK(avx512dq, AVX512DQ);
|
|
CPUID_FEATURE_CHECK(avx512bw, AVX512BW);
|
|
CPUID_FEATURE_CHECK(avx512ifma, AVX512IFMA);
|
|
CPUID_FEATURE_CHECK(avx512vbmi, AVX512VBMI);
|
|
CPUID_FEATURE_CHECK(avx512pf, AVX512PF);
|
|
CPUID_FEATURE_CHECK(avx512er, AVX512ER);
|
|
CPUID_FEATURE_CHECK(avx512vl, AVX512VL);
|
|
CPUID_FEATURE_CHECK(aes, AES);
|
|
CPUID_FEATURE_CHECK(pclmulqdq, PCLMULQDQ);
|
|
|
|
#endif /* !defined(_KERNEL) */
|
|
|
|
/*
|
|
* Detect register set support
|
|
*/
|
|
static inline boolean_t
|
|
__simd_state_enabled(const uint64_t state)
|
|
{
|
|
boolean_t has_osxsave;
|
|
uint64_t xcr0;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_OSXSAVE)
|
|
has_osxsave = !!boot_cpu_has(X86_FEATURE_OSXSAVE);
|
|
#else
|
|
has_osxsave = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_osxsave = __cpuid_has_osxsave();
|
|
#endif
|
|
|
|
if (!has_osxsave)
|
|
return (B_FALSE);
|
|
|
|
xcr0 = xgetbv(0);
|
|
return ((xcr0 & state) == state);
|
|
}
|
|
|
|
#define _XSTATE_SSE_AVX (0x2 | 0x4)
|
|
#define _XSTATE_AVX512 (0xE0 | _XSTATE_SSE_AVX)
|
|
|
|
#define __ymm_enabled() __simd_state_enabled(_XSTATE_SSE_AVX)
|
|
#define __zmm_enabled() __simd_state_enabled(_XSTATE_AVX512)
|
|
|
|
|
|
/*
|
|
* Check if SSE instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_sse_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_XMM));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_sse());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if SSE2 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_sse2_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_XMM2));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_sse2());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if SSE3 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_sse3_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_XMM3));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_sse3());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if SSSE3 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_ssse3_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_SSSE3));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_ssse3());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if SSE4.1 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_sse4_1_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_XMM4_1));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_sse4_1());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if SSE4.2 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_sse4_2_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
return (!!boot_cpu_has(X86_FEATURE_XMM4_2));
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_sse4_2());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if AVX instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_avx_available(void)
|
|
{
|
|
boolean_t has_avx;
|
|
#if defined(_KERNEL)
|
|
has_avx = !!boot_cpu_has(X86_FEATURE_AVX);
|
|
#elif !defined(_KERNEL)
|
|
has_avx = __cpuid_has_avx();
|
|
#endif
|
|
|
|
return (has_avx && __ymm_enabled());
|
|
}
|
|
|
|
/*
|
|
* Check if AVX2 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_avx2_available(void)
|
|
{
|
|
boolean_t has_avx2;
|
|
#if defined(_KERNEL)
|
|
has_avx2 = !!boot_cpu_has(X86_FEATURE_AVX2);
|
|
#elif !defined(_KERNEL)
|
|
has_avx2 = __cpuid_has_avx2();
|
|
#endif
|
|
|
|
return (has_avx2 && __ymm_enabled());
|
|
}
|
|
|
|
/*
|
|
* Check if BMI1 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_bmi1_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_BMI1)
|
|
return (!!boot_cpu_has(X86_FEATURE_BMI1));
|
|
#else
|
|
return (B_FALSE);
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_bmi1());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if BMI2 instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_bmi2_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_BMI2)
|
|
return (!!boot_cpu_has(X86_FEATURE_BMI2));
|
|
#else
|
|
return (B_FALSE);
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_bmi2());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if AES instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_aes_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AES)
|
|
return (!!boot_cpu_has(X86_FEATURE_AES));
|
|
#else
|
|
return (B_FALSE);
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_aes());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if PCLMULQDQ instruction set is available
|
|
*/
|
|
static inline boolean_t
|
|
zfs_pclmulqdq_available(void)
|
|
{
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_PCLMULQDQ)
|
|
return (!!boot_cpu_has(X86_FEATURE_PCLMULQDQ));
|
|
#else
|
|
return (B_FALSE);
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
return (__cpuid_has_pclmulqdq());
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* AVX-512 family of instruction sets:
|
|
*
|
|
* AVX512F Foundation
|
|
* AVX512CD Conflict Detection Instructions
|
|
* AVX512ER Exponential and Reciprocal Instructions
|
|
* AVX512PF Prefetch Instructions
|
|
*
|
|
* AVX512BW Byte and Word Instructions
|
|
* AVX512DQ Double-word and Quadword Instructions
|
|
* AVX512VL Vector Length Extensions
|
|
*
|
|
* AVX512IFMA Integer Fused Multiply Add (Not supported by kernel 4.4)
|
|
* AVX512VBMI Vector Byte Manipulation Instructions
|
|
*/
|
|
|
|
|
|
/* Check if AVX512F instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512f_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512F)
|
|
has_avx512 = !!boot_cpu_has(X86_FEATURE_AVX512F);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512f();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512CD instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512cd_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512CD)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512CD);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512cd();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512ER instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512er_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512ER)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512ER);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512er();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512PF instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512pf_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512PF)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512PF);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512pf();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512BW instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512bw_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512BW)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512BW);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512bw();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512DQ instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512dq_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512DQ)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512DQ);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512dq();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512VL instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512vl_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512VL)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512VL);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512vl();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512IFMA instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512ifma_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512IFMA)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512IFMA);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512ifma();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512VBMI instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512vbmi_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL)
|
|
#if defined(X86_FEATURE_AVX512VBMI)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512VBMI);
|
|
#else
|
|
has_avx512 = B_FALSE;
|
|
#endif
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512f() &&
|
|
__cpuid_has_avx512vbmi();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
#endif /* defined(__x86) */
|
|
|
|
#endif /* _SIMD_X86_H */
|