Enable L2 cache of all (MRU+MFU) metadata but MFU data only
`l2arc_mfuonly` was added to avoid wasting L2 ARC on read-once MRU data and metadata. However it can be useful to cache as much metadata as possible while, at the same time, restricting data cache to MFU buffers only. This patch allow for such behavior by setting `l2arc_mfuonly` to 2 (or higher). The list of possible values is the following: 0: cache both MRU and MFU for both data and metadata; 1: cache only MFU for both data and metadata; 2: cache both MRU and MFU for metadata, but only MFU for data. Reviewed-by: Alexander Motin <mav@FreeBSD.org> Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Gionatan Danti <g.danti@assyoma.it> Closes #16343 Closes #16402
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@ -121,20 +121,26 @@ Controls whether buffers present on special vdevs are eligible for caching
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into L2ARC.
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into L2ARC.
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If set to 1, exclude dbufs on special vdevs from being cached to L2ARC.
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If set to 1, exclude dbufs on special vdevs from being cached to L2ARC.
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.
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.
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.It Sy l2arc_mfuonly Ns = Ns Sy 0 Ns | Ns 1 Pq int
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.It Sy l2arc_mfuonly Ns = Ns Sy 0 Ns | Ns 1 Ns | Ns 2 Pq int
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Controls whether only MFU metadata and data are cached from ARC into L2ARC.
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Controls whether only MFU metadata and data are cached from ARC into L2ARC.
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This may be desired to avoid wasting space on L2ARC when reading/writing large
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This may be desired to avoid wasting space on L2ARC when reading/writing large
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amounts of data that are not expected to be accessed more than once.
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amounts of data that are not expected to be accessed more than once.
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.Pp
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.Pp
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The default is off,
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The default is 0,
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meaning both MRU and MFU data and metadata are cached.
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meaning both MRU and MFU data and metadata are cached.
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When turning off this feature, some MRU buffers will still be present
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When turning off this feature (setting it to 0), some MRU buffers will
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in ARC and eventually cached on L2ARC.
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still be present in ARC and eventually cached on L2ARC.
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.No If Sy l2arc_noprefetch Ns = Ns Sy 0 ,
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.No If Sy l2arc_noprefetch Ns = Ns Sy 0 ,
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some prefetched buffers will be cached to L2ARC, and those might later
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some prefetched buffers will be cached to L2ARC, and those might later
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transition to MRU, in which case the
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transition to MRU, in which case the
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.Sy l2arc_mru_asize No arcstat will not be Sy 0 .
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.Sy l2arc_mru_asize No arcstat will not be Sy 0 .
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.Pp
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.Pp
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Setting it to 1 means to L2 cache only MFU data and metadata.
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.Pp
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Setting it to 2 means to L2 cache all metadata (MRU+MFU) but
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only MFU data (ie: MRU data are not cached). This can be the right setting
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to cache as much metadata as possible even when having high data turnover.
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.Pp
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Regardless of
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Regardless of
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.Sy l2arc_noprefetch ,
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.Sy l2arc_noprefetch ,
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some MFU buffers might be evicted from ARC,
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some MFU buffers might be evicted from ARC,
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@ -9055,12 +9055,17 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz)
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*/
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*/
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for (int pass = 0; pass < L2ARC_FEED_TYPES; pass++) {
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for (int pass = 0; pass < L2ARC_FEED_TYPES; pass++) {
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/*
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/*
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* If pass == 1 or 3, we cache MRU metadata and data
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* pass == 0: MFU meta
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* respectively.
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* pass == 1: MRU meta
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* pass == 2: MFU data
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* pass == 3: MRU data
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*/
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*/
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if (l2arc_mfuonly) {
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if (l2arc_mfuonly == 1) {
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if (pass == 1 || pass == 3)
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if (pass == 1 || pass == 3)
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continue;
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continue;
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} else if (l2arc_mfuonly > 1) {
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if (pass == 3)
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continue;
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}
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}
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uint64_t passed_sz = 0;
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uint64_t passed_sz = 0;
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