Linux ppc64le ieee128 compat: Do not redefine __asm on external headers
There is an external assembly declaration extension in GNU C that glibc uses when building with ieee128 floating point support on ppc64le. Marking that as volatile makes no sense, so the build breaks. It does not make sense to only mark this as volatile on Linux, since if do not want the compiler reordering things on Linux, we do not want the compiler reordering things on any other platform, so we stop treating Linux specially and just manually inline the CPP macro so that we can eliminate it. This should fix the build on ppc64le. Tested-by: @gyakovlev Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Richard Yao <richard.yao@alumni.stonybrook.edu> Closes #14308 Closes #14384
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596cfb6b15
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7319a73921
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@ -26,10 +26,6 @@
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#include <sys/types.h>
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#include <sys/types.h>
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#include <sys/simd.h>
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#include <sys/simd.h>
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#ifdef __linux__
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#define __asm __asm__ __volatile__
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#endif
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#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
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#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
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#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
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#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
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@ -142,7 +138,7 @@ typedef struct v {
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"lvx 19,0,%[SRC2]\n" \
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"lvx 19,0,%[SRC2]\n" \
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@ -172,7 +168,7 @@ typedef struct v {
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: "v18", "v19", "v20", "v21"); \
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: "v18", "v19", "v20", "v21"); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"lvx 19,0,%[SRC2]\n" \
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"lvx 19,0,%[SRC2]\n" \
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@ -189,7 +185,7 @@ typedef struct v {
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: "v18", "v19", "v20", "v21"); \
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: "v18", "v19", "v20", "v21"); \
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break; \
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break; \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 21,0,%[SRC0]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"lvx 20,0,%[SRC1]\n" \
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"vxor " VR0(r) "," VR0(r) ",21\n" \
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"vxor " VR0(r) "," VR0(r) ",21\n" \
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@ -208,7 +204,7 @@ typedef struct v {
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"vxor " VR4(r) "," VR4(r) "," VR0(r) "\n" \
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"vxor " VR4(r) "," VR4(r) "," VR0(r) "\n" \
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"vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
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"vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \
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"vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
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"vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
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@ -217,7 +213,7 @@ typedef struct v {
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: RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
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: RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
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"vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
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"vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
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"vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \
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: UVR2(r), UVR3(r) \
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: UVR2(r), UVR3(r) \
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@ -232,7 +228,7 @@ typedef struct v {
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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"vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
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"vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
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@ -245,7 +241,7 @@ typedef struct v {
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WVR4(r), WVR5(r), WVR6(r), WVR7(r)); \
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WVR4(r), WVR5(r), WVR6(r), WVR7(r)); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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"vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
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"vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \
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@ -253,7 +249,7 @@ typedef struct v {
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: WVR0(r), WVR1(r), WVR2(r), WVR3(r)); \
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: WVR0(r), WVR1(r), WVR2(r), WVR3(r)); \
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break; \
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break; \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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"vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
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: WVR0(r), WVR1(r)); \
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: WVR0(r), WVR1(r)); \
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@ -267,7 +263,7 @@ typedef struct v {
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"vor " VR4(r) "," VR0(r) "," VR0(r) "\n" \
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"vor " VR4(r) "," VR0(r) "," VR0(r) "\n" \
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"vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
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"vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \
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"vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \
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"vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \
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@ -276,7 +272,7 @@ typedef struct v {
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: RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
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: RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \
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"vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \
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"vor " VR3(r) "," VR1(r) "," VR1(r) "\n" \
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"vor " VR3(r) "," VR1(r) "," VR1(r) "\n" \
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: WVR2(r), WVR3(r) \
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: WVR2(r), WVR3(r) \
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@ -291,7 +287,7 @@ typedef struct v {
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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"lvx " VR2(r) " ,0,%[SRC2]\n" \
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"lvx " VR2(r) " ,0,%[SRC2]\n" \
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@ -312,7 +308,7 @@ typedef struct v {
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[SRC7] "r" ((OFFSET(src, 112)))); \
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[SRC7] "r" ((OFFSET(src, 112)))); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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"lvx " VR2(r) " ,0,%[SRC2]\n" \
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"lvx " VR2(r) " ,0,%[SRC2]\n" \
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[SRC3] "r" ((OFFSET(src, 48)))); \
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[SRC3] "r" ((OFFSET(src, 48)))); \
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break; \
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break; \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR0(r) " ,0,%[SRC0]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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"lvx " VR1(r) " ,0,%[SRC1]\n" \
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: WVR0(r), WVR1(r) \
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: WVR0(r), WVR1(r) \
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 8: \
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case 8: \
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__asm( \
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__asm__ __volatile__( \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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"stvx " VR2(r) " ,0,%[DST2]\n" \
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"stvx " VR2(r) " ,0,%[DST2]\n" \
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: "memory"); \
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: "memory"); \
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break; \
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break; \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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"stvx " VR2(r) " ,0,%[DST2]\n" \
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"stvx " VR2(r) " ,0,%[DST2]\n" \
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: "memory"); \
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: "memory"); \
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break; \
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break; \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR0(r) " ,0,%[DST0]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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"stvx " VR1(r) " ,0,%[DST1]\n" \
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: : [DST0] "r" ((OFFSET(dst, 0))), \
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: : [DST0] "r" ((OFFSET(dst, 0))), \
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#define MUL2_SETUP() \
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#define MUL2_SETUP() \
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{ \
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{ \
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__asm( \
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__asm__ __volatile__( \
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"vspltisb " VR(16) ",14\n" \
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"vspltisb " VR(16) ",14\n" \
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"vspltisb " VR(17) ",15\n" \
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"vspltisb " VR(17) ",15\n" \
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"vaddubm " VR(16) "," VR(17) "," VR(16) "\n" \
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"vaddubm " VR(16) "," VR(17) "," VR(16) "\n" \
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 4: \
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case 4: \
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__asm( \
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__asm__ __volatile__( \
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"vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
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"vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
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"vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
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"vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
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"vcmpgtsb 21," VR(17) "," VR2(r) "\n" \
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"vcmpgtsb 21," VR(17) "," VR2(r) "\n" \
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: "v18", "v19", "v20", "v21"); \
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: "v18", "v19", "v20", "v21"); \
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break; \
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break; \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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"vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
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"vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
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"vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
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"vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
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"vand 19,19," VR(16) "\n" \
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"vand 19,19," VR(16) "\n" \
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{ \
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{ \
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switch (REG_CNT(r)) { \
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switch (REG_CNT(r)) { \
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case 2: \
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case 2: \
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__asm( \
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__asm__ __volatile__( \
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/* lts for upper part */ \
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/* lts for upper part */ \
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"vspltisb 15,15\n" \
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"vspltisb 15,15\n" \
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"lvx 10,0,%[lt0]\n" \
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"lvx 10,0,%[lt0]\n" \
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