Implementation of SSE optimized Fletcher-4
Builds off of 1eeb4562 (Implementation of AVX2 optimized Fletcher-4)
This commit adds another implementation of the Fletcher-4 algorithm.
It is automatically selected at module load if it benchmarks higher
than all other available implementations.
The module benchmark was also amended to analyze the performance of
the byteswap-ed version of Fletcher-4, as well as the non-byteswaped
version. The average performance of the two is used to select the
the fastest implementation available on the host system.
Adds a pair of fields to an existing zcommon module parameter:
- zfs_fletcher_4_impl (str)
"sse2" - new SSE2 implementation if available
"ssse3" - new SSSE3 implementation if available
Signed-off-by: Tyler J. Stachecki <stachecki.tyler@gmail.com>
Signed-off-by: Gvozden Neskovic <neskovic@gmail.com>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #4789
This commit is contained in:
Tyler J. Stachecki
Brian Behlendorf
parent
dfbc86309f
commit
35a76a0366
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@ -61,6 +61,14 @@ typedef struct fletcher_4_func {
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const char *name;
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} fletcher_4_ops_t;
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#if defined(HAVE_SSE2)
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extern const fletcher_4_ops_t fletcher_4_sse2_ops;
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#endif
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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extern const fletcher_4_ops_t fletcher_4_ssse3_ops;
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#endif
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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extern const fletcher_4_ops_t fletcher_4_avx2_ops;
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#endif
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@ -23,6 +23,7 @@ KERNEL_C = \
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zfs_deleg.c \
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zfs_fletcher.c \
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zfs_fletcher_intel.c \
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zfs_fletcher_sse.c \
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zfs_namecheck.c \
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zfs_prop.c \
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zfs_uio.c \
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@ -838,11 +838,15 @@ Default value: \fB67,108,864\fR.
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.RS 12n
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Select a fletcher 4 implementation.
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.sp
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Supported selectors are: \fBfastest\fR, \fBscalar\fR, and \fBavx2\fR when
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AVX2 is supported by the processor. If multiple implementations of fletcher 4
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are available the \fBfastest\fR will be chosen using a micro benchmark.
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Selecting \fBscalar\fR results in the original CPU based calculation being
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used, \fBavx2\fR uses the AVX2 vector instructions to compute a fletcher 4.
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Supported selectors are: \fBfastest\fR, \fBscalar\fR, \fBsse2\fR, \fBssse3\fR,
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and \fBavx2\fR. All of the selectors except \fBfastest\fR and \fBscalar\fR
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require instruction set extensions to be available and will only appear if ZFS
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detects that they are present at runtime. If multiple implementations of
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fletcher 4 are available, the \fBfastest\fR will be chosen using a micro
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benchmark. Selecting \fBscalar\fR results in the original CPU based calculation
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being used. Selecting any option other than \fBfastest\fR and \fBscalar\fR
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results in vector instructions from the respective CPU instruction set being
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used.
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.sp
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Default value: \fBfastest\fR.
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.RE
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@ -17,3 +17,4 @@ $(MODULE)-objs += zfs_uio.o
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$(MODULE)-objs += zpool_prop.o
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$(MODULE)-$(CONFIG_X86) += zfs_fletcher_intel.o
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$(MODULE)-$(CONFIG_X86) += zfs_fletcher_sse.o
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@ -149,6 +149,12 @@ static const fletcher_4_ops_t fletcher_4_scalar_ops = {
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static const fletcher_4_ops_t *fletcher_4_algos[] = {
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&fletcher_4_scalar_ops,
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#if defined(HAVE_SSE2)
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&fletcher_4_sse2_ops,
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#endif
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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&fletcher_4_ssse3_ops,
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#endif
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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&fletcher_4_avx2_ops,
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#endif
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@ -157,6 +163,12 @@ static const fletcher_4_ops_t *fletcher_4_algos[] = {
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static enum fletcher_selector {
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FLETCHER_FASTEST = 0,
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FLETCHER_SCALAR,
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#if defined(HAVE_SSE2)
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FLETCHER_SSE2,
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#endif
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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FLETCHER_SSSE3,
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#endif
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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FLETCHER_AVX2,
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#endif
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@ -169,6 +181,12 @@ static struct fletcher_4_impl_selector {
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} fletcher_4_impl_selectors[] = {
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[ FLETCHER_FASTEST ] = { "fastest", NULL },
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[ FLETCHER_SCALAR ] = { "scalar", &fletcher_4_scalar_ops },
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#if defined(HAVE_SSE2)
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[ FLETCHER_SSE2 ] = { "sse2", &fletcher_4_sse2_ops },
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#endif
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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[ FLETCHER_SSSE3 ] = { "ssse3", &fletcher_4_ssse3_ops },
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#endif
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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[ FLETCHER_AVX2 ] = { "avx2", &fletcher_4_avx2_ops },
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#endif
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@ -407,6 +425,7 @@ fletcher_4_init(void)
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ops->init(&zc);
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do {
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ops->compute(databuf, data_size, &zc);
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ops->compute_byteswap(databuf, data_size, &zc);
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run_count++;
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} while (gethrtime() < start + bench_ns);
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if (ops->fini != NULL)
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@ -0,0 +1,205 @@
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/*
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* Implement fast Fletcher4 with SSE2,SSSE3 instructions. (x86)
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*
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* Use the 128-bit SSE2/SSSE3 SIMD instructions and registers to compute
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* Fletcher4 in four incremental 64-bit parallel accumulator streams,
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* and then combine the streams to form the final four checksum words.
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* This implementation is a derivative of the AVX SIMD implementation by
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* James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
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*
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* Copyright (C) 2016 Tyler J. Stachecki.
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*
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* Authors:
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* Tyler J. Stachecki <stachecki.tyler@gmail.com>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(HAVE_SSE2)
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#include <linux/simd_x86.h>
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#include <sys/spa_checksum.h>
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#include <zfs_fletcher.h>
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struct zfs_fletcher_sse_array {
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uint64_t v[2] __attribute__((aligned(16)));
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};
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static void
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fletcher_4_sse2_init(zio_cksum_t *zcp)
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{
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kfpu_begin();
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/* clear sse registers */
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asm volatile("pxor %xmm0, %xmm0");
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asm volatile("pxor %xmm1, %xmm1");
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asm volatile("pxor %xmm2, %xmm2");
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asm volatile("pxor %xmm3, %xmm3");
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}
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static void
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fletcher_4_sse2_fini(zio_cksum_t *zcp)
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{
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struct zfs_fletcher_sse_array a, b, c, d;
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uint64_t A, B, C, D;
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asm volatile("movdqa %%xmm0, %0":"=m" (a.v));
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asm volatile("movdqa %%xmm1, %0":"=m" (b.v));
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asm volatile("psllq $0x2, %xmm2");
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asm volatile("movdqa %%xmm2, %0":"=m" (c.v));
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asm volatile("psllq $0x3, %xmm3");
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asm volatile("movdqa %%xmm3, %0":"=m" (d.v));
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kfpu_end();
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/*
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* The mixing matrix for checksum calculation is:
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* a = a0 + a1
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* b = 2b0 + 2b1 - a1
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* c = 4c0 - b0 + 4c1 -3b1
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* d = 8d0 - 4c0 + 8d1 - 8c1 + b1;
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*
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* c and d are multiplied by 4 and 8, respectively,
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* before spilling the vectors out to memory.
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*/
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A = a.v[0] + a.v[1];
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B = 2*b.v[0] + 2*b.v[1] - a.v[1];
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C = c.v[0] - b.v[0] + c.v[1] - 3*b.v[1];
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D = d.v[0] - c.v[0] + d.v[1] - 2*c.v[1] + b.v[1];
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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static void
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fletcher_4_sse2(const void *buf, uint64_t size, zio_cksum_t *unused)
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{
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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asm volatile("pxor %xmm4, %xmm4");
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for (; ip < ipend; ip += 2) {
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asm volatile("movdqu %0, %%xmm5" :: "m"(*ip));
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asm volatile("movdqa %xmm5, %xmm6");
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asm volatile("punpckldq %xmm4, %xmm5");
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asm volatile("punpckhdq %xmm4, %xmm6");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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asm volatile("paddq %xmm6, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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}
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static void
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fletcher_4_sse2_byteswap(const void *buf, uint64_t size, zio_cksum_t *unused)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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for (; ip < ipend; ip += 2) {
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uint32_t scratch;
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asm volatile("bswapl %0" : "=r"(scratch) : "0"(*ip));
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asm volatile("movd %0, %%xmm5" :: "r"(scratch));
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asm volatile("bswapl %0" : "=r"(scratch) : "0"(*(ip + 1)));
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asm volatile("movd %0, %%xmm6" :: "r"(scratch));
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asm volatile("punpcklqdq %xmm6, %xmm5");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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}
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static boolean_t fletcher_4_sse2_valid(void)
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{
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return (zfs_sse2_available());
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}
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const fletcher_4_ops_t fletcher_4_sse2_ops = {
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.init = fletcher_4_sse2_init,
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.fini = fletcher_4_sse2_fini,
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.compute = fletcher_4_sse2,
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.compute_byteswap = fletcher_4_sse2_byteswap,
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.valid = fletcher_4_sse2_valid,
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.name = "sse2"
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};
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#endif /* defined(HAVE_SSE2) */
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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static void
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fletcher_4_ssse3_byteswap(const void *buf, uint64_t size, zio_cksum_t *unused)
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{
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static const struct zfs_fletcher_sse_array mask = {
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.v = { 0x0405060700010203, 0x0C0D0E0F08090A0B }
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};
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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asm volatile("movdqa %0, %%xmm7"::"m" (mask));
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asm volatile("pxor %xmm4, %xmm4");
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for (; ip < ipend; ip += 2) {
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asm volatile("movdqu %0, %%xmm5"::"m" (*ip));
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asm volatile("pshufb %xmm7, %xmm5");
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asm volatile("movdqa %xmm5, %xmm6");
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asm volatile("punpckldq %xmm4, %xmm5");
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asm volatile("punpckhdq %xmm4, %xmm6");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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asm volatile("paddq %xmm6, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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}
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static boolean_t fletcher_4_ssse3_valid(void)
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{
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return (zfs_sse2_available() && zfs_ssse3_available());
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}
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const fletcher_4_ops_t fletcher_4_ssse3_ops = {
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.init = fletcher_4_sse2_init,
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.fini = fletcher_4_sse2_fini,
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.compute = fletcher_4_sse2,
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.compute_byteswap = fletcher_4_ssse3_byteswap,
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.valid = fletcher_4_ssse3_valid,
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.name = "ssse3"
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};
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#endif /* defined(HAVE_SSE2) && defined(HAVE_SSSE3) */
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