Vectorized fletcher_4 must be 128-bit aligned
The fletcher_4_native() and fletcher_4_byteswap() functions may only safely use the vectorized implementations when the buffer is 128-bit aligned. This is because both the AVX2 and SSE implementations process four 32-bit words per iterations. Fallback to the scalar implementation which only processes a single 32-bit word for unaligned buffers. Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Gvozden Neskovic <neskovic@gmail.com> Issue #4330
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@ -334,7 +334,12 @@ fletcher_4_impl_get(void)
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void
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fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
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{
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const fletcher_4_ops_t *ops = fletcher_4_impl_get();
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const fletcher_4_ops_t *ops;
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if (IS_P2ALIGNED(size, 4 * sizeof (uint32_t)))
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ops = fletcher_4_impl_get();
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else
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ops = &fletcher_4_scalar_ops;
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ops->init(zcp);
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ops->compute(buf, size, zcp);
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@ -345,7 +350,12 @@ fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
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void
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fletcher_4_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
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{
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const fletcher_4_ops_t *ops = fletcher_4_impl_get();
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const fletcher_4_ops_t *ops;
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if (IS_P2ALIGNED(size, 4 * sizeof (uint32_t)))
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ops = fletcher_4_impl_get();
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else
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ops = &fletcher_4_scalar_ops;
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ops->init(zcp);
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ops->compute_byteswap(buf, size, zcp);
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